processor register
英 [ˈprəʊsesə(r) ˈredʒɪstə(r)]
美 [ˈprɑːsesər ˈredʒɪstər]
网络 寄存器; 寄存器窗口; 处理器寄存器
双语例句
- If a D-cache miss ( the processor fails to find data in the D-cache) occurs, an interrupt is raised so that the corresponding register can record this event by increasing its value.
如果发生D-cache失效（处理器无法在D-cache中找到数据），那么发出一个中断，让相应的寄存器可以通过增加它的值记录这一事件。 - Hbr hint_trigger,$ register& This tells the processor that the branch instruction at the relative address hint_trigger is likely to branch to the address specified in register$ register.
hbrhinttrigger，$register&告诉处理器相对地址hinttrigger处的分支指令可能会跳转到寄存器$register所指定的地址。 - Processor utilization resource& PUR register
处理器使用率资源&PUR寄存器 - Whenever memory is accessed in real mode, the physical processor adds the value of the RMO register to the partition's specific real address so that it references a true address in the physical memory.
在采用实模式访问内存时，物理处理器会将RMO寄存器的值与分区特定的实地址相加，以使得它能够引用物理内存中的实地址。 - Its successor was the4040 processor ( released in1974), which had an expanded instruction set, program memory, register set, and stack.
其后面是4040处理器（1974发布），其具有扩展指令集、程序内存、寄存器集和堆栈。 - When two threads are using the same processor, as in the case of Simultaneous Multi-Threading, this register is used to calculate how much physical processor each thread actually utilizes over the same time base.
当两个线程正在使用同一个处理器时，与在同步多线程情况下一样，这个寄存器用于计算每个线程在相同的时间段内实际使用了多少物理处理器。 - The address bus is used by the processor to select aspecific memory location or register within a particular peripheral.
地址总线被处理器用来选择在特定外设中的存储器地址或寄存器。 - The first, a read-modify-write approach, shifts data in the processor register.
首先，读-修改-写步骤，将处理器寄存器中的数据移位。 - When returning from the processor's exception mode, the saved value of T in the SPSR register is used to restore the state.
当模式返回从处理器的异常，对登记保存的值的SPSR中的T是用来恢复状态。 - Processor history register dump area
处理机历史寄存器转储区 - The processor will store the virtual address which caused the page fault in a register, and then signal the operating system through an interrupt handler.
它把导致页面失效的虚拟地址装入寄存器中，再利用中断句柄来通知操作系统。 - Processor local storage address register
处理机本机存储器地址寄存器 - The digit signal processor embodies the center arithmetic logic unit, Multiplier unit, Shifter unit, Sequencing unit, Auxiliary register unit, interception unit.
数字信号处理器包含了中央算术逻辑单元、乘法器单元、移位器单元、排序器单元、辅助寄存器单元、中断单元的设计。 - Based on our study of traditional in-order, decoupled and out-of-order architectures, we proposed the VIM vector processor architecture, which adopts an improved decoupled architecture and distributed register file.
在对已提出的顺序、分离及乱序执行等体系分析比较的基础上，提出了VIM向量协处理器的体系结构并实现了基于VIM体系结构的向量微处理器KD-VIM-1。 - Similar to a classical processor, a programmable quantum processor consists of a fixed quantum gate array, a quantum system as data register and a quantum system as program register.
可程序化量子处理器，像经典处理器一样，由一组门序列和数据寄存器以及程序寄存器组成。 - Experiments show that the lookup capability of network processor can be effectively improved with only a small number of cache entries per processing element. ( 4) A register file and a novel memory hierarchy component, called Split Control Cache, are proposed for network processors.
实验表明，每个处理单元中只要维护少量的缓存表项，就可使网络处理器的查找能力获得有效的提升。（4）提出了一种网络处理器存储子系统中寄存器堆和cache机制的设计方法。 - Based on the NIOS II processor system software design, the use of C language design for the MAC layer controller software modules, including system initialization module, Register processing module, send/ receive control module and WEP processing module.
提出了基于NIOSii处理器系统的软件设计方案，使用C语言设计实现了MAC层控制器的软件部分，其中包括系统初始化模块、寄存器处理模块、发送/接收控制模块等模块。 - Each exceptional interruption of ARM processor corresponds to a jump instruction or sends access instructions to the data evaluated by PC register.
ARM处理器每个异常中断对应一条跳转指令或者向PC寄存器赋值的数据访问指令。 - This method can not only compute the local colorability of interference graphs accurately, but also replace the ad hoc skills of traditional methods by a regular register allocation model. It can thus deal with complex irregular characteristics of embedded processor register files. 2.
此算法不仅可以精确计算冲突图结点是否局部可着色，而且能够用规范的寄存器分配模型代替传统算法中的特殊技巧，以适应嵌入式处理器寄存器文件不规则特征带来的复杂性。